Magnetic random access memory (MRAM) that incorporates a magnetic tunneling junction (MTJ) as a memory storage cell is a strong candidate to provide a high density, fast (1-30 ns read/write speed), and non-volatile storage solution for future memory applications. An MRAM array is generally comprised of an array of parallel first conductive lines on a horizontal plane, an array of parallel second conductive lines on a second horizontal plane spaced above and formed in a direction perpendicular to the first conductive lines, and an MTJ formed at each location where a second conductive line crosses over a first conductive line. A first conductive line may be a word line while a second conductive line is a bit line or vice versa. Alternatively, the first conductive line may be a sectioned line which is a bottom electrode or a stud that connects the MTJ to a transistor.
Referring to FIG. 1, a conventional MRAM structure 1 is shown in which an MTJ 11 is formed between a first conductive line 10 and a second conductive line 12. In this example, the first conductive line is a word line and the second conductive line is a bit line although the terms are interchangeable. A conductive line may also be referred to as a digit line, row line, data line or column line. The word line 10 and bit line 12 are used for writing data into the MTJ 11. The MTJ consists of a stack of layers with a configuration in which two ferromagnetic layers are separated by a thin non-magnetic insulating layer such as Al2O3, AlNXOY, or MgO which is called a tunnel barrier layer. In a so-called bottom pinned layer configuration, the bottom portion 13 is a composite layer with a lower seed layer, a middle anti-ferromagnetic (AFM) layer, and an upper pinned layer. The AFM layer as described in U.S. Pat. No. 5,650,958 is exchange coupled to the pinned layer and thereby fixes the magnetization (magnetic moment) direction of the pinned layer in a preset direction. Above the pinned layer is the tunnel barrier layer 14. The second ferromagnetic layer is a free layer 15 on the tunnel barrier layer and has a magnetization direction which can be changed by external magnetic fields. To maintain data against erasure or thermal agitation, an in-plane uni-axial magnetic anisotropy is needed for the magnetic free layer 15. The top layer in the MTJ 11 is generally a cap layer 16.
In a read operation, the information is read by sensing the magnetic state (resistance level) of the MTJ through a sense current flowing through the MTJ, typically in a current perpendicular to plane (CPP) configuration. When the magnetic vector of the free layer 15 is oriented parallel to that of the pinned layer, there is a lower resistance for current passing through the tunnel barrier layer 14 than when the free layer and pinned layer have magnetic vectors in anti-parallel directions.
During a write operation, an electrical current I1 in bit line 12 and a current I2 in word line 10 yield two magnetic fields on the free layer 15. The magnetic fields conform to a right hand rule so that a first field is generated along a first axis (easy axis) in the plane of the free layer and a second field is produced in a direction orthogonal to the first axis (hard axis) in the free layer. In response to the magnetic field generated by current I1, the magnetic vector in the free layer is oriented in a particular stable direction. The resulting magnetic vector orientation depends on the direction and magnitude of I1 and I2 and the properties and shape of the free layer 15. Generally, writing a zero (0) requires the direction of I1 to be different than when writing a one (1).
One challenge associated with MRAM structures is not to disturb the so-called half selected bits under conductive lines (word line/bit line) that are not intended for programming. The free layer magnetic anisotropy is formed by deviating its shape from a circular shape to an elliptical shape from a top view (not shown). One method to solve the half select bit problem is by increasing the magnetic anisotropy. However, this method will increase the writing current proportionally which is not desired for high density memory devices.
The prior art including U.S. Patent Application 2008/0253178, U.S. Pat. No. 6,335,890, U.S. Pat. No. 6,490,217, U.S. Pat. No. 6,798,690, and U.S. Pat. No. 6,798,691 teach how to solve the half-selected bits issue without greatly increasing the programming current. MTJ cells with a general “C-like” shape can force the magnetization switching along the easy axis into a c-mode which has a much higher coercivity to avoid the half-select bit problem as explained by Y. Zheng et al. in “Switching field variation in patterned submicron magnetic film elements”, J. Appl. Phys. 81(8), 15, p. 5471 (1997).
Another concern related to high density memory is that the transistor size limits the supply of available currents. The magnitude of the magnetic field used to switch the magnetic vector is proportional to the magnitude of I1 and I2. The amplitude of I1 and I2 is on the order of several milli-Amperes for most designs. It is desirable to reduce power consumption and this adjustment is achieved in some cases by increasing the field per current ratio of the conductor. A prior art method for increasing the field per current ratio is to provide a cladding layer on one or more sides of a conductive line. Examples of cladding layers are described by Naji et al. in “A low power 1 Mbit MRAM based on ITIMTJ bit cell integrated with Copper Interconnects”, VLSI Conf. (2002). Other cladding designs are taught in U.S. Pat. No. 5,659,499, U.S. Pat. No. 5,940,319, U.S. Pat. No. 6,211,090, U.S. Pat. No. 6,927,072, U.S. Pat. No. 7,304,360, and in U.S. Pat. No. 7,443,707.
U.S. Pat. No. 6,555,858 teaches the formation of an etch stop layer that is coplanar with a top electrode in a MTJ element before forming a bit line thereon. There is no description of how to control the thickness of the top electrode or the distance between a free layer and an overlying bit line.
Ferromagnetic cladding layers are known to increase the current induced magnetic switching field applied to magnetic elements such as MTJs configured either above or below a metal line having such a cladding layer and thereby reduce the current necessary to produce a switching field. As a result, switching word line transistors can also be made smaller. As the size of MTJs shrinks to 0.1 micron or smaller, the switching fields are expected to become larger and switch transistors will demand a larger amount of chip area.
Referring to FIG. 2, a conventional MRAM 1 with a magnetic cladding design is shown in which a word line 19 is comprised of two parts that are an electrically conductive inner core 10 such as Cu and a soft magnetic cladding layer 17. Likewise, a bit line 20 may be comprised of a copper inner core 12 and a soft magnetic cladding layer 18 formed thereon. The cladding layers are used to focus the magnetic flux associated with and I2 onto MTJ 11 and reduce the magnetic field on the conductive line surfaces which are not facing the MTJ. Ferromagnetic cladding layers are typically made by forming a ferromagnetic layer on one or more sides of a metal line. Note that the cladding layers 17, 18 are not formed on a side of a conductive line that faces the MTJ 11. The magnetization of the cladding layers 17, 18 are along the long axis of the lines 19, 20, respectively, thereby creating poles at both ends of the lines. The fringing field at such poles can reach 50 to 300 Gauss in magnitude.
Referring to FIG. 3, a conventional MRAM is depicted with a stack of MTJ layers 24-29 formed between a bottom electrode 23 and a bit line 30 with a magnetic cladding layer 31. There is a dielectric layer 22 separating the bottom electrode 23 from a word line 20 having a cladding layer 21. In this case, a seed layer 24, AFM layer 25, pinned layer 26, tunnel barrier layer 27, free layer 28, and a capping layer 29 are sequentially formed on bottom electrode 23. The bottom electrode 23 is connected to ground 33 through a transistor 32. Magnetic field strength decreases rapidly as the distance s1 between the free layer 28 and word line 20 increases and as the distance s2 between the free layer and bit line 30 increases. Therefore the spacing s1 and s2 is minimized in order to enhance write efficiency. The spacing s1 and/or s2 must be thin and precisely controlled to reduce the spacing variation that causes write efficiency variation. Thus, it is desirable for the bit line/word line to be deposited on a very flat surface and a capping layer 29 having a well controlled thickness on top of the MTJ stack. U.S. Pat. No. 6,969,895 teaches a method utilizing a CMP process to create a flat surface and capping layer thickness on a MTJ stack for tight and precise control of bit line to free layer spacing thereby allowing the bit line to be placed very close to the free layer in the MTJ stack which maximizes writing efficiency.
Unfortunately, the magnetic interaction between ends 28e of the free layer 28 and regions 31t of the cladding layer 31 proximate to the capping layer 29 can lower the switching threshold which results in high tendency for half-selected bits to be disturbed into the wrong state. When the spacing between the bit line/word line and free layer becomes smaller, this magnetic interaction becomes stronger. This interaction is more pronounced if the MTJ has a c-like shape that is used to increase coercivity and the magnetization switching will not follow c-mode switching. Thus, severe half-select error rates can happen and were indeed observed as shown by the data in FIG. 4 measured from several 4 Mb chips. Line 36 represents one chip based on a “c-like” MTJ design and shows a large error count (EC) was observed after a 1000× bit line write disturb in which a write current was applied 1000 times in ˜10 ns pulses. Therefore, an improved MRAM architecture is needed that solves the half-select bit disturb issue without compromising the high write efficiency of placing a cladded bit line/word line proximate to a free layer in a MTJ.